Field of the Invention
Capacitors are needed in a number of integrated semiconductor circuits, for example, in dynamic random access memory (DRAM) circuits or A/D converters. In many cases, the problem arises to realize a high or sufficient capacitance for the requirements with minimum space occupied. The problem is especially severe in DRAM circuits in which each storage cell has a storage capacitor and a selecting transistor, while the space available for a storage cell is being continuously reduced. At the same time, for reliable storage of the charge and distinguishability of the information to be read, the storage capacitors must retain a certain minimum capacitance. The minimum capacitance is considered to be 25 fF at the present time.
In order to realize the maximum capacitance of the storage capacitor with a given space requirement, among others, trench capacitors are known in which the capacitor electrodes are disposed along the side walls of a trench located in the substrate.
Another cell concept is the so-called stacked capacitor cell in which the capacitor is disposed as a stacked capacitor above the corresponding selecting transistor and mostly also above the bit line. As a result of this, the entire base area of the cell can be utilized for the capacitor and merely sufficient insulation to the neighboring storage capacitor needs to be ensured. This concept has the advantage that it is highly compatible with a logic process.
A storage cell configuration with a stacked capacitor is known from European Patent EP 415 530 B1. The stacked capacitor includes a polysilicon structure with several polysilicon layers disposed essentially parallel on top of one another, connected to one another with a side support. The layers, which are disposed in the manner of radiator ribs, lead to a significant enlargement of the surface of the polysilicon structure in comparison to the projection of the polysilicon structure onto the substrate surface; such a capacitor is mostly called a "fin-stacked capacitor". The polysilicon structure is formed by alternating deposits of polysilicon layers and selectively etchable silicon oxide or carbon layers on the surface of the substrate. Then the layers are structured, producing side coverage (spacer made of polysilicon) on at least one side of the layer structure and selective etching of the silicon oxide or carbon layers. The polysilicon structures are doped with arsenic. Then, a silicon oxide being a capacitor dielectric is formed by thermal oxidation, onto which a cell plate made of doped polysilicon is deposited.
From the European Patent EP 415 530 B1 and an article by Ema et al. in International Electron Devices Meeting, December 1988, p. 592-595, a storage cell configuration with a multi-layer stacked capacitor (called fin-stacked capacitor) is known, which has a central supporting structure with horizontal lamellae surrounding the supporting structure as a storage electrode. The manufacturing method provides that first an insulating layer consisting of silicon oxide and an etch-stop layer be applied above the selecting transistor and then a layer sequence with alternating silicon oxide layers and n-doped polysilicon layers is deposited. Then an opening is made through the layer sequence, the etch-stop layer and the silicon oxide layer all the way to the S/D region of the transistor by etching, filling it with polysilicon, so that, at the same time, the transistor connection and the supporting structure for the polysilicon layers are formed. The layer sequence is structured corresponding to the dimensions of the capacitor and then the SiO.sub.2 layers are removed by a wet method, where the etch-stop layer is necessary to protect the underlying SiO.sub.2 layer. The production of the contact hole is difficult because accurate adjusting to the S/D region is necessary through a number of layers (and three different etching steps are carried out in succession). The etch-stop layer is absolutely necessary, which increases the cost of the process.
In Published, European Patent Application EP 779 656 A2, another manufacturing method is described for a fin-stacked capacitor with an outside supporting structure. A layer structure of alternating p.sup.+ /p.sup.- -doped silicon layers is produced. By etching and opening all the way to the underlying substrate, each layer structure, including the surrounding supporting structure, is separated into two separate partial regions and from each partial region a capacitor is formed which then has a supporting structure on three sides.